Scalable Shared - Memory Architectures

Towards Low-Complexity Scalable Shared-Memory Architectures

Next Generation Internet High-Speed Switches and Routers

Shared memory architecture for packet switches was normally thought to be unsuitable for building high performance switches/routers. The main reason lies in their perceived poor scalability. In particular, shared memory architectures are typically used to build output-queued switches which are regarded as the best candidate to achieve optimal delay-throughput performance. The current trend in r...

Design of a novel congestion-aware communication mechanism for wireless NoC architecture in multicore systems

Hybrid Wireless Network-on-Chip (WNoC) architecture is emerged as a scalable communication structure to mitigate the deficits of traditional NOC architecture for the future Multi-core systems. The hybrid WNoC architecture provides energy efficient, high data rate and flexible communications for NoC architectures. In these architectures, each wireless router is shared by a set of processing core...

OpenMP: An Industry- Standard API for Shared- Memory Programming

46 1070-9924/98/$10.00 © 1998 IEEE IEEE COMPUTATIONAL SCIENCE & ENGINEERING Application developers have long recognized that scalable hardware and software are necessary for parallel scalability in application performance. Both have existed for some time in their lowest common denominator form, and scalable hardware—as physically distributed memories connected through a scalable interconnection...

OpenMP : An Industry - Standard API for Shared - Memory Programming LEONARDO

46 1070-9924/98/$10.00 © 1998 IEEE IEEE COMPUTATIONAL SCIENCE & ENGINEERING Application developers have long recognized that scalable hardware and software are necessary for parallel scalability in application performance. Both have existed for some time in their lowest common denominator form, and scalable hardware—as physically distributed memories connected through a scalable interconnection...